1. Field of the Invention
This invention relates to MOS transistors structures, and in particular to such structures having a gate electrode electrically connected to either a source region or a drain region.
2. Prior Art
MOS transistor structures are well known and widely used. See, for example, U.S. Pat. No. 3,673,471 issued June 27, 1972 to T. Klein, et al. entitled "Doped Semiconductor Electrodes for MOS Type Devices", and assigned to the assignee of this application. Also well known are MOS transistor structures having a gate electrode electrically connected to either a source region or a drain region, which is in turn connected, for example, to a power supply or to another circuit component.
The electrical connection within a single transistor structure between the gate electrode and the source region or between the gate electrode and the drain region has been readily accomplished with a variety of techniques. Because a polycrystalline silicon gate electrode is typically used, however, difficulties have arisen as the connections have usually been accomplished with metal. In prior art devices, that is, a first ohmic connection was formed between a first portion of a metal region and the polycrystalline silicon gate electrode, and a second ohmic connection was formed between a second portion of said metal region and either a source region or a drain region. Consequently, both a metal to polycrystalline silicon connection and a metal to source or drain region electrical connection are required. Prior art devices utilizing this structure typically have several undesirable features.
First, in a typical MOS transistor structure formed on a larger silicon wafer without external connections to other devices or to a power supply, the transistor will occupy a given area of the wafer to a given depth. In some prior art devices the ohmic connection between the metal and the polycrystalline silicon was made external to the area on the wafer which the transistor itself occupied. Thus, additional surface area on the wafer is required both because of the metal connection between the gate electrode and the source or drain region and because the connection itself must occupy some given area. Consequently, the number of devices which will fit within a given area is decreased. This is obviously undesirable as circuits formed from large numbers of such devices occupy more area than is necessary.
A second difficulty occurs when the polycrystalline silicon-metal ohmic connections are not made external to the transistor structure, but are made directly above the area occupied by the transistor gate. For reasons not well understood, but which produce results nonetheless well known, such devices frequently developed shorted gates. They were thus characterized by poor reliability and low manufacturing yields, that is, a lower than desirable ratio of usable devices to devices manufactured.
A third disadvantage of the prior art devices is that extra electrical connections are required. For example, in a transistor unconnected to any other circuit element at least two distinct connections were necessary -- gate electrode to metal, and said metal to either the source region or the drain region. Ideally only a gate electrode to source region or gate electrode to drain region connection would be necessary. The extra connection in prior art devices requires extra surface area on the wafer and complicates manufacture of the devices.
In accordance with the present invention, a semiconductor structure is provided which comprises a substrate of a first conductivity type; first and second regions formed by diffusion in the substrate of opposite conductivity type from the substrate, the first region being laterally separated from the second region; a gate electrode overlying the substrate between the first and second regions and separated from the substrate by insulation, the gate electrode being extended so as to form an ohmic contact with the first region with the gate electrode being insulated from the second region.
In addition, a method of manufacturing a semiconductor structure is provided which comprises the steps of forming an insulating layer over the surface of a semiconductor substrate; defining and etching a first opening in the insulating layer thereby exposing a first area of the surface of the substrate; forming a layer of polycrystalline silicon over the insulating layer and within the first opening; defining and etching an opening in the polycrystalline silicon layer over the first area thereby exposing a portion of the first area such that a portion of the polycrystalline silicon layer remains in contact with the surface of the substrate; defining and etching a second opening in both the insulating layer and the polycrystalline silicon layer thereby exposing a second area of the surface of the substrate; diffusing an impurity into the structure thereby rendering the polycrystalline silicon layer conductive as a gate electrode, and thereby forming first and second regions in the substrate beneath the first and second areas of the surface of the substrate, wherein the gate electrode is formed in ohmic contact with the first region and is insulated from the second region.